3.3 kW GaN totem-pole PFC
A bridgeless totem-pole PFC on 650 V GaN, switching in the MHz class. Predictive dead-time control holds full-load efficiency at 99.1% while keeping current THD low. Schematic, layout and firmware all done in-house.
Projects
Selected builds from the last few years — hardware, firmware and the methodology that holds them together. Each one shipped, was measured on the bench, or both.
22 kW SiC on-board charger
An 800 V on-board charger for an EV powertrain, built around an interleaved CLLC resonant stage with SiC MOSFETs. Maintains soft switching across the full battery-voltage and grid-voltage range. 22 kW continuous in a liquid-cooled package.
Active dv/dt gate driver
A gate driver for SiC MOSFETs that regulates dv/dt at the switch node using segmented gate resistance and closed-loop slew control. It holds overshoot constant across load and temperature. Conceived during my PhD; now filed silicon IP.
WBG EMI testbench
A repeatable EMI characterization bench for WBG converters: automated near-field scanning paired with LISN-based conducted measurements, 30 MHz–1 GHz. Scan positions, analyzer settings and reporting run from one script so every board gets identical treatment.
MHz control firmware
Firmware architecture for converters that switch at MHz rates: a multi-rate ISR structure on DSP C2000, with an FPGA companion providing 20 ns PWM resolution. Fast control loops never wait on slow housekeeping, at any interrupt level.
Layout parasitics playbook
An open playbook of measurement procedures and layout rules for minimizing power-loop inductance in WBG boards. Every rule is tied to a measured nanohenry and a tested layout. Continuously revised as new boards confirm or break the rules.