The layout is the circuit: taming power-loop parasitics

Silicon era design had a convenient fiction: the schematic was the circuit, and the PCB merely connected it. At 100 V/ns and hundreds of amperes per microsecond, that fiction is dead. Every switching event in a wide-bandgap converter is a fight between your semiconductors and the parasitic inductance of the loop they sit in, and the layout — not the schematic — determines who wins. I have reviewed boards where a 40 nH power loop turned a perfectly good 650 V design into a ringing, overshooting machine that failed radiated emissions by 20 dB. Same devices, same control, different copper.

How much inductance are we talking about?

The physics is unforgiving but at least honest. The inductance of a trace over a reference plane can be approximated — and I stress approximated, this is a design tool, not an instrument — by a simple expression:

L ≈ µ0 · l · [ ln(2h / (w + t)) + 0.5 + (w + t) / (6h) ]  /  π
  (henries; l, w, t, h in metres)

Run the numbers and you get the rules of thumb I actually use: a 1 mm wide trace, 35 µm thick, 0.4 mm above a plane carries roughly 0.6–0.8 nH per millimetre of length. A 25 mm power loop with no field cancellation sits around 15–25 nH; the same loop with a vertical return plane can drop below 3 nH. Why does this matter so much? Because the overshoot and ringing at every switching event scale with the energy stored in the loop, ½LI², released into the loop's own resonance with the device output capacitance in a few nanoseconds. At 30 A, cutting the loop from 20 nH to 3 nH removes roughly 90 % of the stored energy — energy that would otherwise appear as drain overshoot, as ringing that couples into every trace within a centimetre, and as EMI across the 30–300 MHz band where conducted-emissions filters are at their weakest.

The single most useful mindset shift: the first layout decision is the return path, not the forward path. Engineers instinctively route the drain-to-capacitor path first and find somewhere for the source return later. Do it backwards. Place the return conductor — the plane or the closely paired track that closes the loop — first, because return placement is what fixes loop area, and loop area is the only variable that matters for both radiated fields and inductance. When I lay out a half-bridge, I start with the vertical structure: switch-node copper on one layer, the DC-link return directly beneath it, and the decoupling capacitors oriented so their own current loops interleave the device loop with opposite orientation. That orientation trick — interleaving parallel legs so their magnetic fields oppose — is field cancellation, and it is the cheapest inductance reduction available: no added parts, no added cost, just geometry chosen with intent.

Vias, antipads, and the details that decide the edge

Vertical transitions are where good layouts quietly accumulate inductance. A single via of 0.3 mm diameter, 1.6 mm long is worth roughly 0.5–0.7 nH; a power loop that must change layers twice through single vias has already added more inductance than a well-designed loop's entire budget. The discipline is mechanical: place vias as an array, close together, so current can fan out instead of crowding through single points; keep antipads small and stitching vias tight to them, because the current returning in a plane crowds toward the via it serves and every millimetre of lateral detour is inductance; never let a power return cross a slot in a reference plane — a slot turns the plane into an inductor and an antenna at the same time. And keep the loop's layer count minimal: every layer transition adds vias and spreads the loop.

Layout rules I never break

• The power loop closes through the decoupling capacitors, not the bulk caps — ceramic caps rated for the ripple current go within millimetres of the devices, oriented for loop cancellation.
• The gate return never shares copper with the power return; kelvin connections from device pads, and the driver sits within millimetres.
• Switch-node copper is a fixed radiation surface, not a convenience — the smallest area that satisfies current density and creepage, and nothing else gets routed near it, especially not sensing or control traces.
• No slots, no antipad fields, and no splits under the power loop's reference plane.
• Parallel devices are interleaved leg-first, not just placed side by side — parallel legs must cancel, not add, or current sharing becomes frequency-dependent.

Measuring the loop honestly

Everything above can be verified, and should be. For loop current and ringing, a coaxial current shunt — resistive element inside a coaxial geometry, placed directly in the loop, bandwidth into the hundreds of MHz — is the honest instrument. The common dishonesty is the humble current probe with a long extension lead, or a Rogowski coil rated for 30 MHz used to observe a 150 MHz ring: the measured envelope looks plausible and the resonant frequency is quietly wrong. For EMI, near-field probing is a localization tool, not a measurement: a loop probe couples to whatever magnetic field is nearest, including the probe's own handle currents, and an H-field peak near the switch node tells you where to look, not what will fail at the antenna. The final truth is a 30 MHz–1 GHz scan with proper LISN impedance, compared against the same measurement on a board where nothing changed but the loop inductance. That comparison, more than any simulation, is how I got my own rules above — and why the layout, in the end, really is the circuit.