GaN gate drivers: the five volts that decide everything — Dr. Camille Dupont

Every time I bring up a new GaN board in the lab, the same thought crosses my mind: the datasheet promises nanosecond switching, but the gate loop has final say. With enhancement-mode GaN HEMTs you are working with a gate that is fully enhanced around 5 V and damaged not far above 6–7 V absolute maximum. There is no 20 V margin like silicon MOSFETs, no ±10 V headroom like SiC. Your entire switching waveform — the thing that decides whether the device turns on in 3 ns or rings for 50 ns — lives inside a window a couple of volts wide. That is why I tell students that with GaN, the gate driver is not a peripheral: it is half the power stage.

The gate loop is a transmission line, like it or not

The real enemy is not the driver IC, it is the inductance between the driver and the gate. A gate loop of 2 nH — which is a compact layout, honestly — at a di/dt of 5 A/µs of gate current looks benign, but during the switching event itself the current through the loop changes in a nanosecond or so. Even a nanohenry gives you volts of gate bounce exactly when you least want them. And because the GaN device has essentially zero gate oxide margin and threshold voltages in the 1–1.5 V range, a 1 V bounce is not a glitch; it is a re-trigger, a shoot-through seed, or a slow, oscillating turn-on edge that multiplies switching loss.

The practical consequences are strict. The driver must sit millimeters from the device — on my boards the driver is placed on the same side of the PCB as the GaN FET, with the gate and return tracks as a tight pair over an unbroken reference plane. Every millimeter of loop length costs you roughly a nanohenry, and every via you force the gate current through is a small antenna. A kelvin-source connection is non-negotiable: the driver's return must land on the source pad of the package or die, never on a power-loop node. If the gate return shares so much as a millimeter of copper with the drain current path, the source of the die bounces relative to your driver ground by L_power·di/dt — commonly several volts — and your carefully regulated 5 V becomes 5 V plus whatever the power loop felt like injecting.

The supply side matters just as much. With a 5 V abs-max gate, I use split rails: a regulated +5 V for turn-on referenced to a clean rail, and a negative rail — I typically run −2 to −3 V — for hold-off. The positive rail needs actual precision, not "approximately 5 V": a supply that sags to 5.5 V under load transients, or overshoots at light load, is eating your lifetime budget. And beware the bootstrap supplies on half-bridge drivers: their ripple rides directly on your gate. If the ripple is more than a few hundred millivolts, filter the high-side supply or use an isolated DC/DC per switch instead. Yes, it costs board area. So does replacing GaN devices.

What actually kills GaN HEMTs

Field failures in my experience cluster into a short, unglamorous list, and almost all of them trace back to the gate loop rather than the silicon (well, the GaN):

Gate overvoltage from ringing or supply drift — a rail that creeps above abs-max, or clamped inductive spikes reflecting through the Miller capacitance into a driver that cannot sink them.
False turn-on from Miller injection at high dv/dt. At 100 V/ns on the switch node, Cgd pumping charge into the gate is not a corner case; it is every switching event. If the gate impedance at that moment is high, dv/dt · Cgd lands as gate voltage. A driver with a low-impedance pull-down (a discrete stage sinking amps, not a 2 Ω IC pin) holds the gate below threshold. A Miller clamp helps when the off-state dv/dt is slow enough for the clamp to engage — but during fast edges the clamp reacts too late, which is precisely when a negative rail is the answer. This is why I consider −2 V not a luxury but part of the gate driver's job description in half-bridges above 100 V.
Source bounce and common-mode transient immunity violations — the high-side driver's ground reference slewing at 100 V/ns; if the driver's CMTI rating is below your actual dv/dt, expect spurious turn-on pulses at exactly the wrong moment. Rate your CMTI with margin against the worst-case edge, not the datasheet typical.
Thermal-driven gate degradation — a driver that runs hot near the device heats the FET's gate path too; GaN gate reliability is strongly temperature-accelerated, so a "5 V forever" rating quietly becomes a shorter-and-shorter rating as the board's thermal design degrades.

Then there is measurement, because half of what people "see" on GaN gates is probe artifact. If you clip a standard probe with its long ground alligator lead onto a gate that is moving in a nanosecond, you will measure ringing that exists only in the probe. The loop formed by the probe ground wire is of order the same inductance as the gate loop you are trying to observe. Use the short ground spring, probe directly on the gate pin, and even then remember the probe capacitance (typically 8–12 pF) is comparable to the gate capacitance of a small GaN device — you are loading the circuit enough to slow the edge you came to measure. My rule: gate measurements on GaN are qualitative unless done with a low-capacitance active probe or a coaxial connection, and cross-checked against drain-edge behavior at reduced bus voltage.

None of this makes GaN fragile — my converters routinely run 650 V devices at switching frequencies that would be absurd in silicon, with hard switching, for years. But the margin that silicon used to silently absorb every layout sin is gone. The five volts that decide everything will treat you exactly as well as your gate loop deserves.